1. Field
The disclosed subject matter is in the field of semiconductor devices and fabrication and, more particularly, semiconductor devices employing split gate memory cells to form non volatile memory.
2. Related Art
Split gate non-volatile memories (NVMs) including, for example, split gate flash devices, provide advantages over stacked-gated devices, in which the control gate is positioned over the floating gate. Split gate flash cells exhibit reduced program disturb for memory cells that are unselected but are either on the selected row or in the alternative on the selected column. Normally cells on the selected row or the selected column are the most likely to exhibit disturb effects regardless of the operation that is being performed on a selected cell. While split gate flash cells have substantially reduced the program disturb problem for cells on the selected rows or columns, split gate flash cells may exhibit a disturb problem with cells on unselected rows and unselected columns. One of the reasons that unselected cells are susceptible in split gate designs is that the particular stress applied to unselected cells is applied for many more cycles than the stress that is applied to cells on a selected row or a selected column.